The present invention relates to a semiconductor integrated circuit device which has a bipolar transistor and a MISFET (Metal-Insulator-Semiconductor Field Effect Transistor). More particularly, it relates to techniques which are effective when applied to a memory device, such as a DRAM (Dynamic Random Access Memory) device or a SRAM (Static Random Access Memory) device having bipolar transistors, particularly both bipolar transistors and MISFETs.
Even more particularly, it relates to a random access memory with high speed and low consumption of power, where a switching circuit as a complex circuit of a bipolar transistor and metal-oxide semiconductor field effect transistor (hereinafter referred to as xe2x80x9cMOSFETxe2x80x9d) is adopted as a peripheral circuit (address circuit, timing circuit or the like) of the memory. Moreover, this invention relates to techniques for isolation between elements of the device.
Generally, the present invention is directed to techniques in semiconductor memories, such as Bi-CMOS (bipolar transistor-complementary metal-oxide-semiconductor structure) memories, to avoid destruction of information due to minority carriers.
Semiconductor memories are manufactured as products of large capacity, such as 64K bits, 256K bits, in recent years. Much developmental work has been done on various semiconductor memories, such as dynamic random access memories (DRAMs) and static random access memories (SRAMs).
The so-called one-MOSFET type memory cell, which is composed of one capacitor for storing information charges and one MOS (Metal-Oxide-Semiconductor) FET for switching, has a small occupation area and is suited to raise the density of integration. Therefore, it is extensively adopted as the memory cell of a DRAM.
In the DRAM, circuits other than a memory cell array, namely, peripheral circuits such as various timing generators, an address buffer circuit, an address decoder circuit, data input/output circuits, a sense amplifier and a main amplifier are constructed of CMOS (Complementary MOS) circuits in each of which an N-channel MOSFET and a P-channel MOSFET are combined. Thus, the DRAM is permitted to exhibit a lower power consumption as well as a higher operating speed and to have a higher density of integration. The DRAM which employs the CMOS circuits for the peripheral circuits is described in, for example, xe2x80x9cNikkei Electronics,xe2x80x9d Jul. 18, 1983, pp. 188-190.
In order to meet the needs of the age for memories of large capacity, investigations have been made from a viewpoint of manufacturing memories with large capacity, high speed and low consumption of power. Illustratively, in order to attain a still higher operating speed and higher integration density, devices constituting a DRAM need to be made smaller, but the magnitudes of signals to be treated decrease with the smaller devices. In order to treat the small signal magnitude at high speed, a high drivability is required of the constituent device of the circuitry. However, insofar as a CMOS circuit is used as the device, the sizes of MOSFETs cannot be made very large from the viewpoint of the density of integration, and the drivability (conductance gm) of each MOSFET is low, so that the operating speed of the memory lowers along with the density of integration. As a result, development of a memory in a mixed state of bipolar transistor and complementary metal-oxide semiconductor field effect transistors (CMOSFET) (the memory being hereinafter referred to as xe2x80x9cBi-CMOS memoryxe2x80x9d), as shown in Japanese patent application No. 22811/1984 (corresponding to U.S. patent application Ser. No. 701,226), has been considered. Specifically, in order to simultaneously achieve the higher density of integration and the higher operating speed, we have made studies of using a bipolar transistor in the peripheral circuit of the DRAM.
FIG. 29 illustrates a fundamental sectional structure of a BI-CMOS system. Of course, the system shown is merely exemplary. Such Bi-CMOS system is stated in detail in xe2x80x9cNikkei Electronicsxe2x80x9d, Aug. 12, 1985, pp. 187-208. Shown in the figure are one n-channel MOS (nMOS) transistor, as well as one p-channel MOS (pMOS) transistor, and an n-p-n bipolar (npnBIP) transistor.
Here, letters S, G and D affixed to the nMOS or pMOS indicate the nodes of the source, gate and drain thereof, respectively, while letters C, E and B affixed to the npnBIP transistor, indicate the nodes of the collector, emitter and base thereof, respectively. Besides, in the figure, diffusion layers have only the impurity types thereof written down for the-sake of brevity. Accordingly, as regards portions to which the same symbols are assigned, it is merely indicated that the conductivity types are the same, and the impurity materials and impurity concentrations are selected at will properly according to the purposes of the portions.
The Bi-CMOS memory will now be described briefly.
In an address circuit, a timing circuit or the like as a peripheral circuit within a semiconductor memory, an output transistor for charging and discharging parasitic capacitance in signal lines of long distance, and an output transistor with large fan-out are constituted by bipolar transistors, and a logical circuit for performing logical processing such as inversion, non-inversion, NAND, NOR is constituted by a CMOS circuit. The logical circuit constituted by the CMOS circuit is of low power consumption, and an output signal of the logical circuit is transmitted through the bipolar output transistor with low output impedance to the signal lines of long distance. Since the output signal is transmitted to the signal lines using the bipolar output transistor with low output impedance, dependence of the signal propagation delay time on the parasitic capacitance of the signal lines can be reduced, whereby a semiconductor memory with low consumption power and high speed is obtained.
However, as discussed further below, problems arise in using bipolar transistors in the peripheral circuits of, for example, the DRAM.
Heretofore, in an integrated circuit employing insulated-gate field effect transistors (hereinafter, abbreviated to xe2x80x9cMOS transistorsxe2x80x9d) or bipolar transistors (hereinafter, abbreviated to xe2x80x9cBIP transistorsxe2x80x9d), isolation among the elements of the integrated circuit has been performed by applying reverse bias voltages to p-n junctions. The details are stated in, for example, xe2x80x9cIntegrated Circuit Technology (1)xe2x80x9d (Corona Publishing Co., Ltd.) by Yanai and Nagata, pp. 21-31. In a Bi-CMOS system, a similar device isolation method similar to the above is adopted.
In such a Bi-CMOS system, in the-prior art, the isolation among a large number of devices within a chip is executed by applying the lowest potential in the circuitry to a p-type substrate (p-Sub) and the highest potential in the circuity to the n-type-isolation-layer (nWELL) for forming the pMOS transistor, whereby the junctions of various parts are prevented from falling into the condition of forward bias. That is, with the prior art, in a case where the circuitry operates between a supply voltage (for example, 5 V) and the earth (0 V), the devices are isolated by applying 0 V to the substrate p-Sub and 5 V to the n-type isolation layer. Since, in such a system, the applied voltage to the substrate p-Sub or to the n-type isolation layer is selected at the lowest voltage required for the device isolation, reverse bias voltages to be applied to the p-n junctions can be rendered small, and therefore it is possible to cope with the problems of lowering in-the breakdown voltages of devices, etc. attendant upon the future microminiaturization of the devices.
In studying Bi-CMOS memories, the inventors have found various modes for destruction of information in the memory. Thus, the inventors have studied the information destruction modes of the information stored in the memory cell of the Bi-CMOS memory, and have found a novel information destruction mode as hereinafter described and have completed one aspect of the present invention as a means for preventing such information destruction.
In addition, the inventors have found that, in a memory device including a bipolar transistor, minority carriers created by the existence of the bipolar transistor incur the so-called soft error in which they invert information stored in a memory cell or information read out from a memory cell to a data line.
The mechanism of the soft error attributed to the bipolar transistor is interpreted as below by way of example.
The switching MOSFET of the memory cell (exemplified by, but not limited to, a DRAM) is constructed of an N-channel MOSFET which is formed within a pxe2x88x92-type substrate. The capacitor of the memory cell has an n+-type semiconductor region being one electrode thereof within the pxe2x88x92-type substrate. Meanwhile, as a desirable device for attaining a high drivability at high speed, a vertical npn-type bipolar transistor is constructed of an n+-type emitter region, a p-type base region, and nxe2x88x92-type and n+-type collector regions within the pxe2x88x92-type substrate. In order to lead the electrode of the collector of this bipolar transistor out of the surface of the substrate, the n+-type buried collector region is formed larger (longer) than the emitter region. For this reason, a potential fluctuation is liable to occur within the buried collector region due to a resistance possessed by itself. The potential fluctuation of the buried collector region causes a pnp-type parasitic bipolar transistor to operate and injects holes into the substrate, to induce a fluctuation in the potential of the substrate. The parasitic bipolar transistor appears with the base region as its emitter region, the buried collector region as-its base region and the substrate as its collector region. On account of the fluctuation of the substrate potential, the substrate is injected with electrons (minority carriers) from an n+-type semiconductor region of high impurity concentration near the parasitic bipolar transistor (for example, the source region or drain region of an N-channel MOSFET). The minority carriers enter the n+-type region of the switching MOSFET and capacitor of the memory cell or the n+-type region of the MOSFET of a sense amplifier or the like, and invert (destroy) information to give rise to the so-called soft error.
Access-time of the DRAM can be shortened by incorporating bipolar transistors into the peripheral circuits. At the same time, however, the soft errors develop conspicuously due to the minority carriers which are created within the substrate by the bipolar transistors or alpha particles. More specifically, the number of times that information passes between a data line and the capacitor increases, to consequently heighten the probability of the minority carriers being trapped particularly in the source region or drain region of the switching MOSFET.
Accordingly, when the bipolar transistors are caused to coexist in the DRAM with the intention of attaining a higher operating speed and a higher density of integration, there is involved the problem that the electrical reliability of the DRAM lowers due to the soft errors.
A further problem addressed by the present invention involves injection of minority carriers arising from application of reverse biasing to provide isolation between semiconductor elements of the integrated circuit device. Since the input or output terminal of an LSI (large-scale integrated circuit) is directly connected with an external circuit, noise above the supply voltage or below 0 V (in general, surge noise such as overshoot or undershoot) might arise. Since the input or output node is connected to the diffusion layer within the chip in any form, the corresponding junction will then be forward-biased in the prior art. By way of example, when the minus surge noise is applied to the n-type diffusion layer indicated at the source S or drain D of the nMOS transistor in FIG. 29, the junction between the n-type diffusion layer and the substrate p-Sub is forward-biased, and a forward current flows from the substrate p-Sub toward the n-type diffusion layer. As a result, minority carriers (electrons in a p-type substrate) are injected into the substrate p-Sub. Since the minority carriers have a mean free path which is usually as long as several hundred xcexcm, they reach another circuit part and incur, for example, the problem that a stored signal in a memory cell is destroyed in an SRAM or DRAM. The phenomenon of the minority carrier injection might be caused not only at the input or output node part, but also by a circuit operation inside the chip in such a manner that the potential of the diffusion layer or of the substrate p-Sub fluctuates locally due to capacitive coupling or due to saturated operation of the bipolar transistor. It is therefore impossible to realize high performance of the Bi-CMOS system.
An object of the present invention is to provide a semiconductor integrated circuit device which is immune against soft errors, which is high in the density of integration and low in power consumption and which is suited to a high speed operation, and a method of manufacturing the same.
Another object of the present invention is to provide a technique which can raise the operating speed and enhance the electrical reliability of a DRAM, or other memory device, having bipolar transistors.
A further object of the invention is to provide a semiconductor memory technique, wherein destruction of storage information caused by use of a Bi-CMOS logic circuit (switching circuit) in peripheral circuitry can be prevented, and also destruction of storage information due to other factors can be prevented.
A still further object of the present invention is to solve the problem arising due to reverse-biasing to provide isolation between elements, and to provide a semiconductor device which operates stably. Another object of the present invention is to provide a voltage application method by which a voltage to be applied to a substrate or an isolation region is freely set according to an intended use, as well as a device structure which makes the method possible.
The aforementioned and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.
Typical ones of the aspects of the present invention disclosed in the present-application will be summarized below.
Under the memory cell of a memory device (illustratively a DRAM) having bipolar transistors and/or under the semiconductor region of the peripheral circuit thereof, a semiconductor region which has the same conductivity type as that of a substrate and an impurity concentration higher than that of the substrate is disposed. That is, a semiconductor region for forming the circuit element of the memory cell, or the semiconductor region of the circuit element of the peripheral circuit, is underlaid with a semiconductor region the conductivity type of which is opposite to that of the former semiconductor region. Moreover, other regions (e.g., a further semiconductor region) can be used in combination with the underlying semiconductor region to act as a shield to prevent minority carriers from entering the memory cell and/or from entering the semiconductor region electrically connected to the bit line. For example, a further semiconductor region can extend from the underlying semiconductor region to the surface of the semiconductor substrate, for example, the underlying semiconductor region and the further semiconductor region together acting as a shield to prevent minority carriers from entering the memory cell and/or bit line.
Thus, where the substrate is of p-type conductivity and the underlying layer is a p+-type buried layer, a p-type region can be provided extending from the p+-type buried layer to the substrate surface to act as such shield. For example, such p-type region can form part of the isolation region between the memory cell and n-type MISFET of the peripheral circuit, the p-type region extending from the p+-buried layer to a field oxide film formed on the semiconductor substrate. Such p-type region, in combination with the underlying p+-buried layer, can act as a shield both for cell mode soft error (e.g., soft error due to introduction of minority carriers into the capacitor of the one-MISFET type memory cell) and bit line mode soft error (e.g., soft error due to minority carriers entering the drain of the switching MISFET of the one-MISFET type memory cell).
As a further illustrative example, the underlying semiconductor region (for example, p+-type buried layer) can be provided to contact a region of opposite conductivity type extending to the substrate surface (for example, an n-type well layer) so as to provide the shielding function.
Such combination of regions (for example, the p+-type buried layer and p-type region; or the p+-type buried layer and n-type well) can act to prevent soft error caused by minority carriers generated by the bipolar transistor (that is, parasitic bipolar transistor action).
In addition, a p+-type buried layer is provided under the drain region of the switching MISFET of the memory cell, and under the MISFET of a sense amplifier of the peripheral circuitry, to avoid bit line mode soft error generated by xcex1-particles.
According to the above expedient, the bipolar transistor is caused to coexist in the peripheral circuit of the DRAM, thereby to attain a higher operating speed, and the underlying semiconductor region and further region form a potential barrier to minority carriers created by the bipolar transistor, thereby to prevent soft errors ascribable to the minority carriers.
A further aspect of the present invention will be set forth. A first carrier absorbing area is formed between a peripheral circuit unit with a Bi-CMOS complex circuit as a switching circuit and a memory cell array unit so as to prevent minority carriers (electrons) from moving. The first carrier absorbing area has a function to reduce the effective current amplification factor of the parasitic bipolar transistor formed between the peripheral circuit unit and the memory cell array unit. As a result, partial destruction of the storage information caused by use of the Bi-CMOS type logical circuit in the peripheral circuit can be prevented.
A still further aspect of the present invention will be set forth. In the present invention, a voltage which is still negative (in general, when a p-type silicon substrate is used) or positive (in general, when an n-type silicon substrate is used) with respect to the operating voltage of circuitry is applied to a portion liable to the injection of minority carriers, for example, a substrate. Further, in the present invention, in order to solve problems ascribable to the method of applying the voltage as stated above, for example, the problem that voltages to be applied to individual devices increase to degrade the reliability of a device of low breakdown voltage such as a microminiature device, the isolation region of MOS transistors of identical conductivity type or bipolar transistors of identical conductivity type is divided into several isolated regions, to which suitable isolation voltages are applied according to the respective uses.